ECEn 424 Review Topics: Chapter 9

---

• Why is virtual memory an important concept? (How does it simplify the task of creating a computer program?)
• What is the overhead of supporting the abstraction of virtual memory, both in software and in hardware?
• What are the similarities and differences between an SRAM cache and main memory in its role as a cache for virtual memory pages from disk? (Consider management, placement, replacement, detecting hits, write policy, miss times, etc.)
• What three states can a virtual page be in?
• What is a page table? (What information is in a typical PTE? Why is the table an essential part of a virtual memory system? How many page tables are there in a system?)
• What is a page fault? How is it detected? How is it handled?
• What are swapping and paging? (What does it mean for a page to be paged out or paged in? What is demand paging? How does paging relate to thrashing?)
• What is the working set of a process?
• How does virtual memory simplify linking, loading, dynamic memory allocation, and inter-process sharing?
• How can the virtual memory mechanism be used to provide memory protection?
• In general, what information is required to translate from virtual to physical addresses? (What must the hardware have access to if it is to do the translation without software assistance?)
• Why are caches generally accessed with physical addresses rather than virtual addresses?
• TLBs
  • What is a TLB, and what role does it play in speeding up address translation?
  • How is a typical TLB organized, and what is stored in each slot in the TLB?
  • Which bits from the virtual address does the TLB use on each access?
  • What information is obtained from the TLB in the case of a TLB hit?
  • What happens in the case of a TLB miss? (Must it be serviced by hardware? By software?)
  • How does TLB size and access time compare with that of L1 caches? (To what extent can the the two accesses be overlapped?)
  • What is the relationship between TLB misses and page faults?
• How are multilevel page tables organized, and how do they save space? (How are they organized in the Intel Core i7 processor running Linux?)
• Does the multilevel nature of a page table increase the complexity of TLB hits? TLB misses? If so, how?
• In general, what kind of information is contained in PTEs in the Core i7? (How big is each entry? What is the significance of the reference and dirty bits, for example? Is there a valid bit?)
• How is the virtual address space for each Linux process organized? What is found in the kernel virtual memory?
• When a page fault is detected, how does the Linux exception handler determine if the access is a legal access? (What role do the kernel's "area" or "segment" data structures play in this? What information is maintained in each "area" structs?)
• What is memory mapping? (How is it employed by the kernel in implementing fork and execve calls? How can it be employed by user-level code? When does data actually get copied?)
• What mechanisms are used to allow the heap to grow larger during execution? (How are additional pages within the virtual memory space allocated?)
• What are the responsibilities of the runtime allocator each time malloc and free are called?
• What are common memory-related bugs in C programs?
• Self test: Can you complete all practice problems in Chapter 10?

Updated for 3rd Edition of CS:APP