ECEn 324 Review Topics: Chapter 4
ECEn 324 Review Topics: Chapter 4
- What are the essential characteristics of the Y86 ISA?
- What are the main differences between the Y86 and the x86 and why
did the Y86 designers make those changes?
- How do the Y86 and x86 fit into the RISC vs. CISC debate?
- What tools exist (used in class labs) that allow us to run Y86
programs?
- How is HCL used to represent fundamental building blocks?
- What are clocked registers and what are the important
characteristics of their operation?
- What components are required to implement a processor?
- What is the natural sequence of operations performed in the
execution of a single instruction?
- What kinds of control signals must be generated in the execution
of a single instruction?
- General pipelining topics:
- What performance improvement can result from pipelining?
- What are the advantages and disadvantages of increasing the
pipeline length?
- How are throughput and latency defined in the
context of a pipeline?
- Why are data and control dependences major concerns in a
pipelined CPU?
- What hardware modifications are required to pipeline a CPU?
- What are the pipeline stages in the pipelined implementation of
Y86?
- Why is branch prediction so important in pipelined CPUs, and what
prediction methods can be employed?
- Are all instructions that alter the flow of control equally
difficult to predict or are some worse than others?
- Why do hazards arise and what options exist for dealing
with them?
- Can data hazards arise on accesses to memory or accesses to the
condition codes?
- What hardware is required for forwarding?
- Can forwarding eliminate all stalls on integer instructions? On
FP instructions?
- In general, what types of control signals must be generated to
control the pipeline?
- Under what conditions must the pipeline be stalled?
- What special challenges do exceptions present in the operation of
a pipeline?
- How are the effects of inefficiencies in the pipeline quantified?
- How is the CPI computed and what values are reasonable for 5-stage pipelines?
- What additional factors must be considered that arise in a
pipeline due to multicycle instructions and the memory system interface?
- Self test: Given time and necessary resources, could you complete
all practice problems in Chapter 4?
Updated for 2nd Edition of CS:APP