ECEn 424 Review Topics: Chapter 4
ECEn 424 Review Topics: Chapter 4
Updated for 3rd Edition of CS:APP
- What are the essential characteristics of the Y86-64 ISA?
- What are the main differences between the Y86-64 and the x86-64
and why did the Y86-64 designers make those changes?
- How do the Y86-64 and x86 architectures fit into the RISC
vs. CISC debate?
- What tools exist (used in class labs) that allow us to run Y86-64
- How is HCL used to represent fundamental building blocks?
- What are clocked registers and what are the important
characteristics of their operation?
- What components are required to implement a processor?
- What is the natural sequence of operations performed in the
execution of a single Y86-64 instruction?
- What kinds of control signals must be generated in the execution
of a single instruction?
- Given a table of the steps required to process an unnamed Y86-64
instruction, can you identify the instruction?
- General pipelining topics:
- What performance improvement can result from pipelining?
- What are the advantages and disadvantages of increasing the
- How are throughput and latency defined in the
context of a pipeline?
- Why are data and control dependences major concerns in a
- What hardware modifications are required to pipeline a CPU?
- What are the pipeline stages in the pipelined implementation of
- Why is branch prediction so important in pipelined CPUs, and what
prediction methods can be employed?
- Are all instructions that alter the flow of control equally
difficult to predict or are some worse than others?
- Why do hazards arise and what options exist for dealing
- Can data hazards arise on accesses to memory or accesses to the
- What hardware is required for forwarding?
- Can forwarding eliminate all stalls on integer instructions? On
- In general, what types of control signals must be generated to
control the pipeline?
- Under what conditions must the pipeline be stalled?
- What special challenges do exceptions present in the operation of
- How are exceptions handled in the PIPE processor described in the
- How are the effects of inefficiencies in the pipeline quantified?
- How is the CPI computed and what values are reasonable for 5-stage pipelines?
- What additional factors must be considered that arise in a
pipeline due to multicycle instructions and the memory system
- Topics from supplemental material (see the class slides)
- What other hazards arise when multi-cycle FP instructions
are added to the instruction set?
- What additional functional units does a modern CPU have that
were not present in the Y86-64, and how are they integrated into
- What is the relationship of dependencies, hazards, and
- What are the consequences of using a deep pipeline to
implement a processor?
- What is the key idea behind a superscalar processor
and what special design challenges does this present?
- How do branch history tables, branch target buffers, and
tournament predictors work?
- What is the fundamental idea behind dynamic
scheduling and what hardware changes are required to support
- In the dynamically scheduled CPU described in the class
slides (and modeled in Lab 5), how were RAW hazards, WAW hazards
and mispredicated branches handled, and how were precise exceptions
- Self test: Given time and necessary resources, could you complete
all practice problems in Chapter 4?